{"id":89,"date":"2016-04-20T08:44:39","date_gmt":"2016-04-20T07:44:39","guid":{"rendered":"http:\/\/www.i3a.uclm.es\/raap\/?page_id=89"},"modified":"2017-03-27T12:58:03","modified_gmt":"2017-03-27T11:58:03","slug":"project-1","status":"publish","type":"page","link":"https:\/\/www.i3a.uclm.es\/raap\/?page_id=89","title":{"rendered":"Increasing on-chip network efficiency for improving the performance of chip multiprocessors supporting simultaneous parallel applications"},"content":{"rendered":"

Funded by Junta de Comunidades de Castilla-La Mancha. PEII-2014-028-P\u00a0and European Commission (FEDER funds) (2014-2017).<\/h3>\n

Current semiconductor manufacturing techniques allow to include multiple\u00a0cores on the same chip. This has been used by the microprocessor industry to\u00a0keep increasing the computing speed, favouring multicore chips instead of an\u00a0increasingly powerful uniprocessor. Power consumption, heat dissipation,\u00a0or cost are some of the main concerns against the latter, motivating that\u00a0decision. Although these cores do not necessarily run as fast as the highest\u00a0performing single-core processors, they all together improve the overall\u00a0performance. Therefore, chips containing tens or even hundreds of identical\u00a0cores are expected in the future. Chip Multiprocessors (CMPs) are an\u00a0excellent example of these systems.<\/p>\n

\"Slimfly\"<\/p>\n

To take full advantage of CMPs, it is also expected that several\u00a0applications will run simultaneously on such CMP systems. Moreover, as the
\nnumber of cores is likely to increase, it is expected that the number of\u00a0applications to run in the same CMP will also increase. In this scenario,
\nall resources in the CMP are shared by the applications. If resource\u00a0allocation is not managed in an efficient way, performance of any individual
\napplication can be seriously affected. All CMP components have an important\u00a0role in the CMP performance. Cores, caches, memory controllers, and the
\ninterconnection network must be carefully designed to contribute to\u00a0applications reaching their required performance levels.<\/p>\n

This project focuses on the interconnection network (network-on-chip or simply\u00a0NoC, in the CMP context). Since current and future applications running on
\nCMPs can be of diverse nature\u00a0(e.g. computer vision, media processing, animation, simulations, data
\nmining, etc.), the global traffic pattern can be completely\u00a0unpredictable because of the different program behaviors for different
\nexternal inputs. Consequently, it is much more difficult to manage network\u00a0traffic if several applications coexist in the same CMP. In this scenario,
\nthe network traffic interferences between applications increase and the\u00a0performance of individual applications can suffer an important degradation.<\/p>\n

On the other hand, due to the increasing number of cores, congestion\u00a0situations will be more likely to happen in future CMP systems. As these
\nsituations may lead to a severe network performance degradation, it would be\u00a0interesting to have efficient congestion management techniques oriented to
\nkeep CMP performance even in congestion situations.<\/p>\n

New techniques will be proposed with\u00a0the aim of improving network global performance, thereby also improving the
\nperformance of individual applications when they simultaneously run in the\u00a0CMP. Resource virtualization, quality of service and congestion management
\ntechniques, considering electrical and photonic technologies, are explored\u00a0to achieve such objective.<\/p>\n","protected":false},"excerpt":{"rendered":"

Funded by Junta de Comunidades de Castilla-La Mancha. PEII-2014-028-P\u00a0and European Commission (FEDER funds) (2014-2017). Current semiconductor manufacturing techniques allow to include multiple\u00a0cores on the same chip. This has been used by the microprocessor industry to\u00a0keep increasing the computing speed, favouring multicore chips instead of an\u00a0increasingly powerful uniprocessor. Power consumption, heat dissipation,\u00a0or cost are some of the main concerns against the latter, motivating that\u00a0decision. Although these cores do not necessarily run as fast as the highest\u00a0performing single-core processors, they all together improve the overall\u00a0performance. Therefore, chips containing tens or even hundreds…<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":13,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-89","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.i3a.uclm.es\/raap\/index.php?rest_route=\/wp\/v2\/pages\/89","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.i3a.uclm.es\/raap\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.i3a.uclm.es\/raap\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.i3a.uclm.es\/raap\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.i3a.uclm.es\/raap\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=89"}],"version-history":[{"count":9,"href":"https:\/\/www.i3a.uclm.es\/raap\/index.php?rest_route=\/wp\/v2\/pages\/89\/revisions"}],"predecessor-version":[{"id":685,"href":"https:\/\/www.i3a.uclm.es\/raap\/index.php?rest_route=\/wp\/v2\/pages\/89\/revisions\/685"}],"up":[{"embeddable":true,"href":"https:\/\/www.i3a.uclm.es\/raap\/index.php?rest_route=\/wp\/v2\/pages\/13"}],"wp:attachment":[{"href":"https:\/\/www.i3a.uclm.es\/raap\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=89"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}